1. Field of the Invention
The present invention relates to a DRAM (Dynamic Random Access Memory) for performing a read modify write process.
2. Description of the Related Art
Conventionally, a DRAM control circuit for performing a read modify write process comprises a DRAM controller and a DRAM. The DRAM controller receives an address, write data, and data rewrite command from a host controller. The DRAM controller designates a row address and a column address to the DRAM. In addition, the DRAM controller causes the signal levels of a row address strobe signal, a column address strobe signal, and a read signal to become "L". After the DRAM controller reads the contents of the address through a data bus, the DRAM controller causes the signal level of the read signal to become "H" level and subsequently the write signal to "L" level, then transmits write data to the DRAM.
On the other hand, when the signal levels of a row address strobe terminal, a column address strobe terminal, and an output enable terminal of the DRAM are "L", the DRAM controller outputs the content of the address designated from the input/output terminal to the data bus. When the signal level of the read/write terminal is "L", the DRAM controller inputs the write data to the DRAM through the input/output terminal through the data bus and rewrites the content of the designated address with the write data.
However, a commercial DRAM is designed so that the output enable terminal is grounded. (Refer to "HB56G51232 Series, Hitachi IC Memory Data Book 3", Semiconductor Division, Hitachi Co., Ltd., 14-th edition, pp. 922-924, 1992.
Thus, in the DRAM control circuit, after a read cycle, although a row address and a column address were designated, the signal level of the output enable terminal of the DRAM is "L". Thus, the data bus cannot be switched for the data write operation. After the read cycle, the DRAM controller causes the signal levels of the row address strobe signal and the column address strobe signal to become "L", designates the row address and the column address to the DRAM, and causes the signal level of the write signal to become "L", and rewrites the content of the address of the DRAM with the write data. Thus, the number of cycles of the read modify write process becomes long.